In an effort to optimize and create improved analog devices, attention has been made to the improving of trimming procedures and techniques. In modern trimming techniques, a standardized semiconductor industry device known as an Electrically Erasable Programmable Ready Only Memory (EEPROM) device is often utilized. Such EEPROM devices can be configured in various manners, such as in single or double polysilicon structures, single or double bit structures, and/or distributive-gate arrangements.
Since the ultra-thin oxides used for electron tunneling into the first polysilicon layer of double polysilicon layered EEPROM devices generally cannot be grown on the N+ regions of the device with typical technologies and processes, single polysilicon structures (single poly) in EEPROM devices are often utilized. In addition, many EEPROM devices utilize a distributive-gate configuration that can generally be manufactured through standard CMOS semiconductor processes without expensive process modifications. Non-distributive or other standard EEPROM devices require expensive process step changes and modifications during manufacturing.
With reference to FIGS. 1A and 1B, representative diagrams a of a top view and a cross-sectional view of a conventional single-poly, distributive EEPROM device 100 are illustrated. The continuous single-poly configuration of EEPROM cell 100 is configured to provide three devices. In the center of EEPROM device 100, an NMOS device comprises a READ transistor 104. The right side of EEPROM device 100 comprises a capacitor 102 having a fork-shaped poly structure with an underlying SNWELL providing a control gate 108 configured to provide a WRITE (W) input. The left side of EEPROM device 100 includes a tunneling region 106 configured to provide an ERASE (E) input. The magnitude of the voltage for the programming WRITE (W) and ERASE (E) pulses can be critical to operation of EEPROM cell 100 during calibration of an analog circuit.
The programming voltage of distributive EEPROM device 100 is determined by the thickness of the gate oxide underneath tunneling region 106 of EEPROM device 100. For standard CMOS processes, this oxide thickness is the same as that of the oxide used by the control logic CMOS transistors of the analog integrated circuit device to be trimmed or calibrated. Because the oxide used for programming voltages is the same oxide used on the control CMOS transistors, the programming voltage is developed by importing a high voltage power source from outside the analog integrated circuit, such as a 12V input supply for a conventional 5V CMOS analog circuit. As a result, an analog circuit using an EEPROM device for calibration can only be calibrated or trimmed typically during probe or final test operation at the manufacturer's location, as opposed to after packaging and/or after customer printed circuit board mounting.
In addition, current precision analog integrated circuits have become very susceptible to physical stress mis-calibration, such as that occurring after final testing at the manufacturer's location. For example, since silicon is a piezoelectric material, any strain placed on the silicon, whether from the plastic packaging or from mounting the integrated circuit to the printed circuit board, often results in mis-calibration. Accordingly, a need has arisen to provide for a mechanism and technique to provide for re-programming of the precision analog integrated circuit device after packaging and/or after customer printed circuit board mounting. Such internal re-programming must be accomplished through the on-chip transistors and on-chip power supplies. However, standard distributive EEPROM devices generally require approximately 10 volts for programming of a 5V CMOS analog circuit, making such EEPROM devices unsuitable for programming by on-chip devices.